Elevated voltage and/or thermal stresses are applied to integrated circuit chips (IC) during qualification testing to determine if the ICs will remain functional for 10 years in the field. The stress time needed to project 10 year IC reliability depends upon the stress voltage and stress temperature applied to the IC during accelerated testing. For example an IC that needs to survive at 80° C. for 10 years may be stress tested for 6 months with a stress temperature of 100° C. or for a shorter period of time if a more elevated stress temperature is used (ie. 120° C.). Similarly an IC that operates at a power supply voltage of 1 volt may be stress tested for 6 months with a stress voltage of 1.25 volts or may be tested for a shorter time if the stress voltage more elevated (ie. 1.5 volts). Typically ICs are tested with elevated stress temperature and with elevated stress voltage during qualification testing to reduce testing time.
The accelerated testing time interval may be many weeks or many months. The accelerated stress testing is typically interrupted at predetermined testing points distributed throughout the qualification testing time to determine if any failures have occurred. The frequency of testing points is typically higher at the beginning of the qualification test and end of the qualification test to determine if the failure rate is higher during these periods of testing. Conventional stress testing does not determine if multiple IC failures occurred randomly throughout the interval between testing points or if they occurred simultaneously at one time somewhere within the interval.
A typical testing setup is illustrated in FIG. 1. A burn-in board 104 (or burn-in mother board) is populated with ICs 106 to be accelerated stress tested. The burn-in board 104 populated with ICs 106 is plugged into a communication socket 110 inside an burn-in oven 108. A driver interface board 102 is plugged into the communication socket 110 outside the burn-in oven 108. A computer (PC) 100 is connected to the driver interface board 102 to control the accelerated stress testing.
An example accelerated testing protocol is illustrated in FIG. 2.
In step 200 the burn-in mother board 104 is populated with packaged ICs 106 to be tested. Usually all the IC's 106 on the burn-in mother board 104 are the same.
In step 202 the burn-in mother board 104 is plugged into the communication socket 110 in the burn-in oven 108. The temperature of the burn-in oven 108 is then raised to the target thermal stress temperature.
In step 204 the computer 100 sends signals to the driver interface board 102 to begin testing. The computer may also communicate with the burn-in oven 108 to set the stress temperature. The driver interface board then powers up the burn-in mother board so that the packaged IC's become functional and may apply an elevated stress voltage to the ICs under test to initiate the accelerated testing.
In step 206, the PC 100 stops the test when a predetermined testing point (time) is reached.
In step 208 the motherboard is removed from the oven.
In step 210 the packaged ICs are removed from the motherboard and tested for failure. Automated Testing Equipment (ATE) may be used to determine functionality of the ICs 106.
Step 212 checks to see if the testing is complete. If testing is not complete the ICs 106 are plugged back into the burn-in mother board 104 in step 200 and another cycle of stress testing is initiated.
When the stress testing is complete, the stress testing is discontinued and the test is ended in step 214.